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MCP3202
2.7V Dual Channel 12-Bit A/D Converter with SPI(R) Serial Interface
FEATURES
* * * * * * * * * * * 12-bit resolution 1 LSB max DNL 1 LSB max INL (MCP3202-B) 2 LSB max INL (MCP3202-C) Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI(R) serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V - 5.5V 100ksps max. sampling rate at VDD = 5V 50ksps max. sampling rate at VDD = 2.7V Low power CMOS technology - 500nA typical standby current, 5A max. - 550A max. active current at 5V Industrial temp range: -40C to +85C 8-pin PDIP SOIC and TSSOP packages
PACKAGE TYPES
PDIP
CS/SHDN CH0 CH1 VSS
1 2 3 4
8 7 6 5
VDD/VREF CLK DOUT DIN
MCP3202
SOIC, TSSOP
CS/SHDN CH0 CH1 VSS
* *
1 2 3 4
8 7 6 5
MCP3202
VDD/VREF CLK DOUT DIN
APPLICATIONS
* * * * Sensor Interface Process Control Data Acquisition Battery Operated Systems
FUNCTIONAL BLOCK DIAGRAM
VDD VSS
DESCRIPTION
The Microchip Technology Inc. MCP3202 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3202 is programmable to provide a single pseudo-differential input pair or dual single-ended inputs. Differential Nonlinearity (DNL) is specified at 1 LSB, and Integral Nonlinearity (INL) is offered in 1 LSB (MCP3202-B) and 2 LSB (MCP3202-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 100ksps at 5V and 50ksps at 2.7V. The MCP3202 device operates over a broad voltage range (2.7V 5.5V). Low current design permits operation with typical standby and active currents of only 500nA and 375A, respectively. The MCP3202 is offered in 8-pin PDIP, TSSOP and 150mil SOIC packages.
CH0 CH1 Input Channel Mux DAC Comparator Sample and Hold Control Logic 12-Bit SAR
Shift Register
CS/SHDN
DIN
CLK
DOUT
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 1
MCP3202
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
PIN FUNCTION TABLE
NAME VDD/VREF CH0 CH1 CLK DIN DOUT CS/SHDN FUNCTION +2.7V to 5.5V Power Supply and Reference Voltage Input Channel 0 Analog Input Channel 1 Analog Input Serial Clock Serial Data In Serial Data Out Chip Select/Shutdown Input
VDD.........................................................................7.0V All inputs and outputs w.r.t. VSS ...... -0.6V to VDD +0.6V Storage temperature ..........................-65C to +150C Ambient temp. with power applied......-65C to +125C Soldering temperature of leads (10 seconds) .. +300C ESD protection on all pins ...................................> 4kV
*Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40C to +85C, fSAMPLE = 100ksps and fCLK = 18*fSAMPLE unless otherwise noted. PARAMETER Conversion Rate Conversion Time Analog Input Sample Time Throughput Rate DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion (SINAD) Spurious Free Dynamic Range Analog Inputs Input Voltage Range for CH0 or CH1 in Single-Ended Mode Input Voltage Range for IN+ in Pseudo-Differential Mode Input Voltage Range for IN- in Pseudo-Differential Mode Leakage Current Switch Resistance Sample Capacitor RSS CSAMPLE VSS INVSS-100 .001 1K 20 VREF VREF+INVSS+100 1 mV A pF See Figure 4-1 See Figure 4-1 V See Sections 3.1 and 4.1 See Sections 3.1 and 4.1 -82 72 86 dB dB dB VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz VIN = 0.1V to 4.9V@1kHz INL DNL 12 0.75 1 0.5 1.25 1.25 1 2 1 3 5 bits LSB LSB LSB LSB LSB MCP3202-B MCP3202-C No missing codes over temperature tCONV tSAMPLE fSAMPLE 1.5 100 50 12 clock cycles clock cycles ksps ksps VDD = VREF = 5V VDD = VREF = 2.7V SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
DS21034A-page 2
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
ELECTRICAL CHARACTERISTICS (CONTINUED)
All parameters apply at VDD = 5.5V, VSS = 0V, TAMB = -40C to +85C, fSAMPLE = 100ksps and fCLK = 18*fSAMPLE unless otherwise noted. PARAMETER Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements Operating Voltage Operating Current Standby Current VDD IDD IDDS 2.7 375 0.5 5.5 550 5 V A A VDD = 5.0V, DOUT unloaded CS = VDD = 5.0V fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF 500 100 100 250 250 100 50 50 200 200 100 1.8 0.9 MHz MHz ns ns ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 Note 1 VDD = 5V (Note 2) VDD = 2.7V (Note 2) VIH VIL VOH VOL ILI ILO CIN, COUT -10 -10 4.1 0.4 10 10 10 Straight Binary 0.7 VDD 0.3 VDD V V V V A A pF IOH = -1mA, VDD = 4.5V IOL = 1mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TAMB = 25C, f = 1 MHz SYMBOL MIN. TYP. MAX. UNITS CONDITIONS
Note 1: This parameter is guaranteed by characterization and not 100% tested. Note 2: Because the sample cap will eventually lose charge, effective clock rates below 10kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 for more information.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 3
MCP3202
tCSH CS tSUCS tHI CLK tSU DIN tHD tLO
MSB IN tEN tDO NULL BIT MSB OUT tR tF LSB tDIS
DOUT
FIGURE 1-1:
Serial Timing.
Load circuit for tR, tF, tDO
1.4V 3K DOUT CL = 100pF Test Point DOUT
Load circuit for tDIS and tEN
Test Point VDD 3K 100pF VSS VDD/2
tDIS Waveform 2 tEN Waveform tDIS Waveform 1
Voltage Waveforms for tR, tF
DOUT VOH VOL
Voltage Waveforms for tEN
CS 1 CLK DOUT 2 3 4 B11
tR
tF
tEN Voltage Waveforms for tDO
CLK
Voltage Waveforms for tDIS
CS VIH 90% TDIS DOUT Waveform 2 10%
tDO
DOUT
DOUT Waveform 1*
* Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control.
FIGURE 1-2:
Test Circuits.
DS21034A-page 4
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
2.0 TYPICAL PERFORMANCE CHARACTERISTICS
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25
2.0
Positive INL
INL (LSB)
INL (LSB)
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0
V DD = 2.7V Positive INL
Negative INL
Negative INL
50
75
100
125
150
20
40
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-1: Rate.
Integral Nonlinearity (INL) vs. Sample
FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V).
1.0 0.8 0.6
Positive INL FSAMPLE = 100ksps
1.0 0.8 0.6 0.4
Positive INL FSAMPLE = 50ksps
INL (LSB)
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.5 4.0 4.5 5.0
Negative INL
INL (LSB)
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0
Negative INL
VDD(V)
VDD(V)
FIGURE 2-2:
Integral Nonlinearity (INL) vs. VDD.
FIGURE 2-5:
Integral Nonlinearity (INL) vs. VDD.
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0
VDD = 2.7V FSAMPLE = 50ksps
INL (LSB)
INL (LSB)
512 1024 1536 2048 2560 3072 3584 4096
Digital Code
Digital Code
FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 5
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative INL Positive INL
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative INL VDD = 2.7V F SAMPLE = 50ksps Positive INL
INL (LSB)
INL (LSB)
Temperature (C)
Temperature (C)
FIGURE 2-7: Temperature.
Integral
Nonlinearity
(INL)
vs.
FIGURE 2-10: Integral Nonlinearity Temperature (VDD = 2.7V).
(INL)
vs.
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25
2.0 1.5 1.0
Positive DNL
V DD = 2.7V
DNL (LSB)
DNL (LSB)
0.5 0.0 -0.5 -1.0 -1.5 -2.0
Positive DNL
Negative DNL
Negative DNL
50
75
100
125
150
0
20
40
60
80
100
Sample Rate (ksps)
Sample Rate (ksps)
FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V).
1.0 0.8 0.6
Positive DNL FSAMPLE = 100ksps
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
2.5 3.0 3.5 4.0 4.5 5.0
Negative DNL Positive DNL FSAMPLE = 50ksps
DNL (LSB)
0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0
Negative DNL
DNL (LSB)
0.4
2.5
3.0
3.5
4.0
4.5
5.0
VDD(V)
VDD(V)
FIGURE 2-9:
Differential Nonlinearity (DNL) vs. VDD.
FIGURE 2-12: Differential Nonlinearity (DNL) vs. VDD.
DS21034A-page 6
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096
VDD = 2.7V F SAMPLE = 50ksps
Digital Code
DNL (LSB)
DNL (LSB)
Digital Code
FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V).
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative DNL
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
Negative DNL VDD = 2.7V FSAMPLE = 50ksps Positive DNL
DNL (LSB)
DNL (LSB)
Positive DNL
Temperature (C)
Temperature (C)
FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V).
2.0 1.5
2.0 1.8
F SAMPLE = 10ksps
Offset Error (LSB)
Gain Error (LSB)
1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 2.5 3.0
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
FSAMPLE = 100ksps
FSAMPLE = 50ksps
FSAMPLE = 10ksps
F SAMPLE = 100ksps
F SAMPLE = 50ksps
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD(V)
VDD(V)
FIGURE 2-15: Gain Error vs. VDD.
FIGURE 2-18: Offset Error vs. VDD.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 7
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25C
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100
VDD = 5V FSAMPLE = 100ksps
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100
VDD = 2.7V F SAMPLE = 50ksps
Offset Error (LSB)
Gain Error (LSB)
VDD = 2.7V FSAMPLE = 50ksps
VDD = 5V F SAMPLE = 100ksps
Temperature (C)
Temperature (C)
FIGURE 2-19: Gain Error vs. Temperature.
FIGURE 2-22: Offset Error vs. Temperature.
100 90 80 70 60 50 40 30 20 10 0 1 10 100
VDD = 2.7V FSAMPLE = 50ksps VDD = 5V FSAMPLE = 100ksps
100 90 80
VDD = 5V FSAMPLE = 100ksps
SINAD (dB)
SNR (dB)
70 60 50 40 30 20 10 0 1 10 100
VDD = 2.7V FSAMPLE = 50ksps
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency.
FIGURE 2-23: Signal to Noise and Distortion (SINAD) vs. Input Frequency.
0 -10 -20 -40 -50 -60 -70 -80 -90 -100 1 10 100
VDD = 5V FSAMPLE = 100ksps
80 70
VDD = 5V F SAMPLE = 100ksps
SINAD (dB)
THD (dB)
-30
VDD = 2.7V FSAMPLE = 50ksps
60 50 40 30 20 10 0 -40 -35 -30 -25 -20 -15 -10 -5 0
VDD = 2.7V FSAMPLE = 50ksps
Input Frequency (kHz)
Input Signal Level (dB)
FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Signal Level.
DS21034A-page 8
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25C
12.0
F SAMPLE = 50ksps
12.0 11.5
VDD = 5V FSAMPLE = 100ksps
11.5
ENOB (rms)
11.0 10.5 10.0 9.5 9.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
F SAMPLE = 100ksps
ENOB (rms)
11.0 10.5 10.0 9.5 9.0 8.5 8.0 1 10 100
VDD = 2.7V FSAMPLE = 50ksps
VDD (V)
Input Frequency (kHz)
FIGURE 2-25: Effective number of bits (ENOB) vs. VDD.
FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
100 90 80 70 60 50 40 30 20 10 0 1 10 100
VDD = 2.7V FSAMPLE = 50ksps
0
Power Supply Rejection (dB)
VDD = 5V FSAMPLE = 100ksps
-10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000
SFDR (dB)
Input Frequency (kHz)
Ripple Frequency (kHz)
FIGURE 2-26: Spurious Free (SFDR) vs. Input Frequency.
Dynamic
Range
FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 30000
VDD = 5V FSAMPLE = 100ksps
Amplitude (dB)
40000
50000
Amplitude (dB)
FINPUT = 9.985kHz 4096 points
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 15000
VDD = 2.7V FSAMPLE = 50ksps FINPUT = 998.76Hz 4096 points
20000
25000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-27: Frequency Spectrum of 10kHz input (Representative Part).
FIGURE 2-30: Frequency Spectrum of 1kHz input (Representative Part, VDD = 2.7V).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 9
MCP3202
Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100ksps, fCLK = 18* fSAMPLE,TA = 25C
500 450 400 350 300 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
All points at F CLK = 1.8MHz except at VDD = 2.5V, F CLK = 900kHz
80 70 60
CS = VDD
IDDS (pA)
IDD (A)
50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
VDD (V)
FIGURE 2-31: IDD vs. VDD.
FIGURE 2-34: IDDS vs. VDD.
500 450 400 350
VDD = 5V
100.00
VDD = CS = 5V
10.00
IDD (A)
250 200 150 100 50 0 10 100 1000 10000
VDD = 2.7V
IDDS (nA)
300
1.00
0.10
0.01 -50 -25 0 25 50 75 100
Clock Frequency (kHz)
Temperature (C)
FIGURE 2-32: IDD vs. Clock Frequency.
FIGURE 2-35: IDDS vs. Temperature.
500
2.0
Analog Input Leakage (nA)
450 400 350
VDD = 5V F CLK = 1.8MHz
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100
VDD = 5V FCLK = 1.8MHz
IDD (A)
300 250 200 150 100 50 0 -50 -25 0 25 50 75 100
VDD = 2.7V FCLK = 900kHz
Temperature (C)
Temperature (C)
FIGURE 2-33: IDD vs. Temperature.
FIGURE 2-36: Analog Input leakage current vs. Temperature.
DS21034A-page 10
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
3.0
3.1
PIN DESCRIPTIONS
CH0/CH1
4.1
Analog Inputs
Analog inputs for channels 0 and 1 respectively. These channels can programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN-. See Section 5.0 for information on programming the channel configuration.
3.2
CS/SHDN(Chip Select/Shutdown)
The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions.
The MCP3202 device offers the choice of using the analog input channels configured as two single-ended inputs or a single pseudo-differential input. Configuration is done as part of the serial command before each conversion begins. When used in the psuedo-differential mode, CH0 and CH1 are programmed as the IN+ and IN- inputs as part of the command string transmitted to the device. The IN+ input can range from IN- to VREF (VREF + IN-). The IN- input is limited to 100mV from the VSS rail. The IN- input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN- inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN-, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VREF + (IN-)] - 1 LSB}, then the output code will be FFFh. If the voltage level at IN- is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VREF level.
3.3
CLK (Serial Clock)
The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed.
3.4
DIN (Serial Data Input)
The SPI port serial data input pin is used to clock in input channel configuration data.
3.5
DOUT (Serial Data output)
The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place.
4.0
DEVICE OPERATION
The MCP3202 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100ksps are possible on the MCP3202. See Section 6.2 for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface.
4.2
Digital Output Code
The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3202, VDD is used as the reference voltage. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below.
Digital Output Code = 4096 * VIN VDD
where:
VIN = analog input voltage VDD = supply voltage
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 11
MCP3202
VDD VT = 0.6V Sampling Switch SS RSS = 1k CSAMPLE = DAC capacitance = 20 pF VSS
Legend VA = Signal Source RS = Source Impedance CHx = Input Channel Pad CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions SS = Sampling Switch RSS = Sampling Switch Resistor CSAMPLE = Sample/Hold Capacitance
RS
CHx CPIN 7pF
VA
VT = 0.6V
ILEAKAGE 1nA
FIGURE 4-1:
Analog Input Model.
Clock Frequency (MHz)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 1000
VDD = 5V
VDD = 2.7V
10000
Input Resistance (Ohms)
FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions.
DS21034A-page 12
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
5.0
5.1
SERIAL COMMUNICATIONS
Overview
Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in pseudo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is low, then the data will come from the device in MSB first format and any further clocks with CS low will cause the device to output zeros. If the MSBF bit is high, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. See Figure 5-2. Table 5-1 shows the configuration bits for the MCP3202. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 12 clocks will output the result of the conversion with
MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, (and MSBF = 1), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 for more details on using the MCP3202 devices with hardware SPI ports.
CONFIG BITS SGL/ DIFF SINGLE ENDED MODE PSEUDODIFFERENTIAL MODE 1 1 0 0 ODD/ SIGN 0 1 0 1
CHANNEL SELECTION 0 + + IN+ INININ+ 1
GND
-
TABLE 5-1:
Configuration Bits for the MCP3202.
tCYC tCSH CS tSUCS CLK
tCYC
DIN
Start SGL/ ODD/ MS DIFF SIGN BF
Don't Care
Start SGL/ ODD/ DIFF SIGN
DOUT
HI-Z
Null Bit B11
HI-Z
B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
tSAMPLE
tCONV tDATA**
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 below for details on obtaining LSB first data. ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 13
MCP3202
FIGURE 5-1: Communication with the MCP3202 using MSB first format only.
tCYC tCSH CS tSUCS CLK
Power Down
MSBF
Start
ODD/ SIGN
SGL/ DIFF
DIN
Don't Care
DOUT
HI-Z
HI-Z Null * B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Bit (MSB)
tSAMPLE
tCONV
tDATA **
* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
FIGURE 5-2:
Communication with MCP3202 using LSB first format.
DS21034A-page 14
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
6.0
6.1
APPLICATIONS INFORMATION
Using the MCP3202 with Microcontroller (MCU) SPI Ports
which requires that the SCLK from the MCU idles in the `low' state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the `high' state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains seven leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCU receive buffer will contain three unknown bits (the output is at high impedance until the null bit is clocked out), the null bit and the highest order four bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method.
With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually done by sending `leading zeros' before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 6-2 show how the MCP3202 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode 0,0,
CS
MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Data is clocked out of A/D Converter on falling edges
DIN
Start
SGL/ DIFF
MSBF
ODD/ SIGN
Don't Care
DOUT
HI-Z
NULL BIT B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Start Bit MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X X X X X X X X 1 SGL/ ODD/ MSBF DIFF SIGN X X X X X X X X X X X X X
X
X
X
X
X
X
X
X
X
X
0 B11 (Null)
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X = Don't Care Bits
Data stored into MCU receive register after transmission of first 8 bits
Data stored into MCU receive register after transmission of second 8 bits
Data stored into MCU receive register after transmission of last 8 bits
FIGURE 6-1:
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
CS
MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
Data is clocked out of A/D Converter on falling edges
DIN
Start
MSBF
ODD/ SIGN
SGL/ DIFF
Don't Care
DOUT
HI-Z
NULL BIT B11 Start Bit
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock)
0
0
0
0
0
0
0
1
SGL/ ODD/ MSBF DIFF SIGN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0 B11 (Null)
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X = Don't Care Bits
Data stored into MCU receive register after transmission of first 8 bits
Data stored into MCU receive register after transmission of second 8 bits
Data stored into MCU receive register after transmission of last 8 bits
FIGURE 6-2:
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 15
MCP3202
6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations
When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2ms (effective clock frequency of 10kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 1F is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688 "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection
6.3
Buffering/Filtering the Analog Inputs
If the signal source for the A/D Converter is not a low impedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive the analog input of the MCP3202. This amplifier provides a low impedance output for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Low pass (anti-aliasing) filters can be designed using Microchip's interactive FilterLabTM software. FilterLab will calculate capacitor and resistor values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 "Anti-Aliasing Analog Filters for Data Acquisition Systems." VDD
4.096V Reference
0.1F ADI REF198 1F Tant. 0.1F 10uF Device 1
Device 4
Device 3 Device 2
FIGURE 6-4: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths.
VREF IN+
1F
MCP3202
R1 C1 R2 C2 R3 R4 MCP601 IN-
VIN
+ -
FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order anti-aliasing filter for the signal being converted by the MCP3202.
FilterLab is a trademark of Microchip Technology Inc. in the U.S.A and other countries. All rights reserved.
DS21034A-page 16
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
MCP3202 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCP3202 - G T /P
Package:
P = PDIP (8 lead) SN = SOIC (150 mil Body), 8 lead ST = TSSOP, 8 lead (C Grade only) I = -40C to +85C
Temperature Range: Performance Grade: Device:
B = 1 LSB INL (TSSOP not available in this grade) C = 2 LSB INL MCP3202 = 12-Bit Serial A/D Converter MCP3202T = 12-Bit Serial A/D Converter on tape and reel (SOIC and TSSOP packages only)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. After September 1, 1999 (480) 786-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 17
MCP3202
NOTES:
DS21034A-page 18
Preliminary
(c) 1999 Microchip Technology Inc.
MCP3202
NOTES:
(c) 1999 Microchip Technology Inc.
Preliminary
DS21034A-page 19
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DS21034A-page 20
(c) 1999 Microchip Technology Inc.

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